1. Field of the Invention
The present invention relates to a power amplifier MMIC used primarily in a mobile communication terminal.
2. Related Art of the Invention
In recent years, digital mobile communications have been spreading rapidly, and development of mobile terminals is vigorously under way. In the development of terminals, reductions in size, weight, and cost are strongly demanded. Size and cost reductions are also needed for radio circuitry and, among others, reducing the size and cost of power amplifiers is a key point. In digital mobile telephones, power amplifier modules using discrete semiconductor devices and chip components are mainly used as their power amplifiers. Size reduction can be achieved by fabricating the power amplifier in the form of an MMIC (Monolithic Microwave Integrated Circuit) on a semiconductor substrate. When fabricating a three-stage amplifier on a semiconductor, however, the IC chip size greatly varies depending on the arrangement of the three transistors. In a power amplifier MMIC, the semiconductor chip size is the predominant determinant of the cost. Therefore, efficient arrangement of the transistors becomes a key factor for the realization of a low cost MMIC.
A prior art power amplifier MMIC will be described below with reference to FIGS. 4 to 6. FIG. 4 is a circuit schematic diagram showing a conventional three-stage power amplifier MMIC. In FIG. 4, reference numeral 1100 is a semiconductor substrate, 1101 is an input terminal, 1102 is a first matching circuit, 1103 is a first transistor, 1104 is a second matching circuit, 1105 is a second transistor, 1106 is a third matching circuit, 1107 is a third transistor, 1108 is the gate terminal of the third transistor, 1109 is an output terminal, 1111 is a package lead array, and 1113 is a fourth matching circuit.
As shown in FIG. 4, the first matching circuit 1102 is connected to the gate terminal of the first transistor 1103, the second matching circuit 1104 is connected between the drain terminal of the first transistor 1103 and the gate terminal of the second transistor 1105, the third matching circuit 1106 is connected between the drain terminal of the second transistor 1105 and the gate terminal 1108 of the third transistor, and the fourth matching circuit 1113 is connected, via the package lead array 1111, to the output terminal 1109 leading from the drain terminal of the third transistor 1107. With this configuration, each matching circuit derives the desired output in the desired frequency band, and the amplifier is thus adjusted so that the desired gain can be obtained.
FIG. 5 shows an example of the power amplifier fabricated in MMIC form. In FIG. 5, reference numeral 1200 is the semiconductor substrate, 1201 is the input terminal, 1202 is the first matching circuit, 1203 is the first transistor, 1204 is the second matching circuit, 1205 is the second transistor, 1206 is the third matching circuit, 1207(a) is a transistor as one half of the third transistor, 1207(b) is a transistor as the other half of the third transistor, 1208(a) is the gate terminal of the one half 1207(a) of the third transistor, 1208(b) is the gate terminal of the other half 1207(b) of the third transistor, and 1209 is an output terminal array. In the power amplifier, as is generally the case with this type of power amplifier, the transistor size increases exponentially in the order of the first transistor 1203, the second transistor 1205, and the third transistor 1207(a) and (b), as shown in FIG. 5. As a result, if these transistors are simply arranged side by side as shown in FIG. 5, the unused space of the semiconductor substrate increases, which not only hinders the reduction of chip size but also increases the cost.
In FIG. 5, the third transistor is divided into two parts; in general practice, a transistor for high output power amplification is constructed by arranging small power transistors in parallel as shown here. A detailed description of such transistors will not be given here; for details, one should refer to Chapter 5 "High Output GaAs FETS" in "Fundamentals of GaAs Field Effect Transistors," Fukuda, Hirachi et al., The Institute of Electronics, Information and Communication Engineers.
FIG. 6 shows an example of the MMIC with improved layout.
In FIG. 6, reference numeral 1300 is a semiconductor substrate, 1301 is the input terminal, 1302 is the first matching circuit, 1303 is the first transistor, 1304 is the second matching circuit, 1305 is the second transistor, 1306 is the third matching circuit, 1307(a) is a transistor as one half of the third transistor, 1307(b) is a transistor as the other half of the third transistor, 1308(a) is the gate terminal of the one half 1307(a) of the third transistor, 1308(b) is the gate terminal of the other half 1307(b) of the third transistor, 1309 is an output terminal array, 1310 is a package formed from a dielectric material, 1311 is the package lead array, 1312 is an output line, and 1313 is the fourth matching circuit.
Reduction in the chip size can be achieved by connecting the input terminal 1301, the first matching circuit 1302, the first transistor 1303, the second matching circuit 1304, the second transistor 1305, and the third matching 1306 in a vertical array alongside the third transistor 1307(a) and (b), as shown in FIG. 6. This layout method is also used in "An E-Mode GaAs FET Power Amplifier MMIC for GSM Phones," W. Abey et al., IEEE MTT-S Digest, pp. 1315-1318, 1997, and will not be described in detail here.
With the power amplifier MMIC layout shown in FIG. 6, however, if the desired power value is to be obtained, input signals must be applied to the gate terminals of the third transistor 1307(a) and (b) by aligning the amplitude and phase between the signals, and signals from all the output terminals 1309 must be output and combined by aligning them in amplitude and phase. However, to align the amplitude and phase between the input signals applied to the gate terminals 1308(a) and 1308(b) of the third transistor 1307(a) and (b), the output of the third matching circuit 1306 must be divided symmetrically between the two halves of the third transistor 1307(a) and (b), as shown in FIG. 6. In that case, the output of the third matching circuit 1306 must be brought out and signal lines be routed to the respective centers of the third transistor 1307(a) and (b). The resulting problem is that a space that cannot be used for other circuitry is created between the third transistor 1307(a) and (b) and the vertical array of the input terminal 1301, the first matching circuit 1302, the first transistor 1303, the second matching circuit 1304, the second transistor 1305, and the third matching 1306.